A UCLA-led paper reports a 2.6× geometric-mean speedup over direct RTL design across 11 FPGA tasks by having agents work first at a higher-level hardware abstraction, then refine the synthesized RTL. The paper was submitted September 17; its code and evaluation artifacts are public. Paper, repository
The important idea is the division of labor. High-level synthesis carries decades of transformation knowledge, leaving the model to make choices in a representation where useful changes are easier to express. Lower-level refinement can recover optimization opportunities afterward. The 2.6× result applies to this benchmark suite. A good local test would hold time and assistance constant on one known numerical kernel, score correctness separately from performance, and examine the cases that resist the method. Those boundaries are where a paper becomes an engineering workflow.